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OPTIMUM Series Model 200-VLSI High Pin Count Burn-In System

The OPTIMUM 200-VLSI currently has the highest number of independent test channels available in a monitored burn-in system. The system has up to 512 independent I/O. Each test tray incorporates "distributed test architecture". This means that each test position operates completely independent of any other tray in the system. This is accomplished through the integration of pattern generators, voltage regulators, fault latch circuitry, fault image capture RAM etc. on each burn-in position. In systems of this nature, where the electronics cost is high, it is very important that the customer gets maximum use of the hardware. Independent test capability at each position provides the maximum flexibility and system usage.

The system is currently available with either 32K or 128K vector depth. The pattern generator provides two nested loops with 64K count each for nested looping operations. Further, with our process control software module (OPCTL) patterns can be downloaded in Page Mode. This incremental download is limited only by the device pause characteristics and the size of the hard drive. Operating speeds vary between 2.5 and 10 Mhz depending on the configuration and operating mode. The OPTIMUM 200-VLSI utilizes a 32 bit data bus. This speeds up the lengthy process of downloading patterns via serial interfaces that are currently available. Pattern conversion utilities are available for most popular ATE and Simulators.

The electronics architecture provides a fault image capture RAM that operates in two modes. The first mode provides a capture of device response data. This can be compared to expected results for pass/fail determination. The second mode acts as a fault mask for care/don't care testing. The modes can be combined to capture the device outputs and using them as a fault mask. This combined operation provides for a learning feature. A logic analyzer screen function provides graphical images of the vector RAM, image/fault capture RAM.

The system is available with signaling for standard CMOS (to 6 volts) and low/high voltage applications (1.5 to 10 Volts). Up to 16 clocks are configurable to any channel on the interface. Our high speed timing generator provides timing resolution of 25 nSec. The current configurations provide basic timing out of the vector RAM. Any channel can be defined through software as clocks, addresses, data I/O etc.

The system utilizes a high pin count interface (720 mechanical I/O) to achieve the signal count. Full power and ground planes are provided to insure signal integrity. The chambers are Nitrogen Purged to protect device leads from oxidation.

Future enhancements can include parametric channels for Iddq testing, forced guard option, analog channels for mixed signal devices and additional independent clocks.

This system currently leads the industry in pin count and overall flexibility. This is truly the state of the art in high pin count, functional burn-in (TDBI).