OPTIMUM Series Model 200-CT Parametric Measurement System, Memories

The OPTIMUM 200-CT burn-in system has been designed to specifically address parametric and functional testing in a burn-in environment. By utilizing an PMU through an IEEE interface, we can measure a wide variety of parametric measurements. The main emphasis of this system is for functional and Iddq measurements. The parallel nature of burn-in systems provide a reasonable test bed for Quiescent Current Measurements, where test times are a severe limitation for standard ATE.

The OPTIMUM 200-IDDQ is a fully monitored test burn-in system for memory products with the emphasis on SRAM and non-Volatile memories. The design requirement for this system was to provide a functional test capability and the integration of parametric test functions. A relay multiplexer is used at each driver card location to distribute the parametric measurement (Iddq) function. Up to 32 measurement channels are provided per burn-in board location.

Each electronics position consists of independent voltage regulators, fault cache, comparators and OPTIMUM control interface, parametric measurement mux and RAM based Programmable Pattern Generator. A one to one Driver Board to Pattern Generator ratio is provided. The pattern generators are algorithmic providing all standard patterns through N2. A single Keithley force measurement is utilized on an IEEE interface for the parametric function.

The system performance is based on a 40 MHz main oscillator. This provides 100 nSec timing resolution. Rise and Fall times are typically less than 60 nSec. Signal levels can vary between 1.5 and 10 volts providing test flexibility for future low voltage devices as well as all existing CMOS technology. A graphical interface has been provided for entry of timing sets improving previous entry methods that did not allow relational data entry.

The system consists of 32 chip selects, 32 Data I/O, 8 OE, 8 R/W, 24 address and 32 Parametric Channels. All input signals are looped back to insure integrity.

Alternate pattern generators can be used to "reconfigure" the system function for logic device. This "logic" pattern generator is non-algorithmic and provides up to 128K of random vector depth. Further, patterns can be converted from either ATE (Schlumberger, LTX, etc.) or source (Mentor Graphics, etc.) pattern files.


OPTIMUM Series Model 200-CT-CMR-SRAM Cold Memory TDBI System

The OPTIMUM 200 CT-CMR burn-in system has been designed to specifically address functional and cold memory retention testing of SRAMs. This system is provided with a hot/cold chamber (either LN2 or Mechanical refrigeration). Through the use of our OPCTL process control and test language, system parameters are varied time sequentially and automatically to perform a specific test flow. There are no real limitations to the number of test steps available. So, for example, program PPG, lower temperature, pause, read devices, download patterns etc. All addressable functions can be controlled in this manner (example comparators can be programmed for automatic DUT margining. The OPCTL function is available on all OPTIMUM systems.

Each electronics position consists of independent voltage regulators, fault cache, comparators and OPTIMUM control interface and RAM-based pattern generator. A one to one Driver Board to Pattern Generator ratio is provided. The pattern generators are algorithmic providing all standard patterns through N2.

The system performance is based on a 40 MHz main oscillator. This provides 100 nSec timing resolution. Rise and Fall times are typically less than 60 nSec. Signal levels can vary between 2 and 6 volts providing test flexibility for most existing CMOS technology. A graphical interface has been provided for entry of timing sets, improving previous entry methods that did not allow relational data entry.

The system consists of 32 chip selects, 32 Data I/O, 8 OE, 8 R/W and 24 address. All input signals are looped back to insure integrity.

This system uses an IC driver for cost reduction. This limits the voltage swing necessary for clocking of low voltage parts.