Model 200-SEM High Performance Memory TDBI System

The OPTIMUM 200-SEM is one of the most sophisticated burn-in systems developed for both engineering and production test applications.  With a high speed timing generator and local processor at each burn-in board location, it represents the state-of-the-art in Test During Burn-In (TDBI) for semiconductor memory products.  The system has been developed for high density memory testing in a burn-in environment.  The system provides functional verification of DRAMs, SRAMs, EPROMs, etc.

Each electronics position consists of independent voltage regulators, a fault cache for failed address and data bit capture, comparators, optional local processor (8680) with PMU for data analysis and local hardware control, Algol PG and OPTIMUM control interface.   Each burn-in board location has complete electrical independence from any other in the system.  The pattern generators are algorimic providing all standard patterns through N3/2

The system performance is based on an 100 MHz main oscillator.  This provides 10nSec pulse width timing resolution.  The minimum cycle time is 100nSec.   Address Rise and Fall times are typically 20 nSec with a typical <5 nSec skew across the test board.  A 1.5 nSec edge vernier adjusts pulse edges to within 1.5 nSec resolution.  Signal levels can vary between (Vih)1.5 to  and (Vil) -1.5 to 5 volts providing test flexibility for future low voltage devices and all existing CMOS technology.  A graphical interface has been provided for entry of timing sets improving previous entry methods that did not allow relational data entry.

The system has 208 driver interface channels: 32 chip selects, 128 Data I/O, 18 clocks (RAS, WE, etc.) 30 addresses.  16 bit Data In word is supplied to the 128 I/O interface.  All input signals are looped back to ensure integrity.  The signal configuration provides testing of DRAMs to 1G x and SRAMs to 1G x.  Address scrambling is provided on row and column boundaries with logical formatting of data on address state.

An optional local processor is used to control the logical progression associated with many test processes for parallel processing of each test position.  For example, soft error analysis and cold memory retention testing may be performed in parallel at different test locations.  By controlling the functions locally, the time usually associated for analysis of complicated functions such as those described is substantially reduced.

Because this system is a full, functional TDBI system, failed address/bit analysis is provided.  Optional statistical analysis and post processing software is available to perform Schmoo Plotting, Weibul Analysis, Lognormal, Exponential, etc.  Cumulative failures are also collected for QRA applications (i.e. optimal burn-in calculations).   Over 1000 cumulative fail maps may be collected during a test cycle.  Each stores complete data pertinent to the test.  As with all OPTIMUM systems, multiple chambers and zones can be integrated under one system controller.  For production, this means centralized control and optional CIM integration.  For engineering or QRA applications, multiple chamber types can be integrated for specific tasks.  For example, small chambers for different thermal zones or temperature cycling protocols.